1. Field of the Invention
The present invention relates to wiring layout systems for integrated circuits and, more specifically, to a system that minimizes creation of jogs during the masking process.
2. Description of the Prior Art
The process of designing an integrated circuit involves many different levels of abstraction, beginning with the functional specification of the circuit and ending with the layout of regions of dopants, polysilicon and metals on the actual crystal that makes up the circuit. At one level, a auto router wiring tool specifies the routes that wires will take to connect to shapes (such as vias, etc.). After the wiring tool lays out all of the wiring for a chip, a masking tool will create the masks that are used in depositing the materials that form the circuit onto crystal face of the chip.
The masking tool employs a series of rules to maintain the integrity of the chip. Some of these rules are based on the technology being employed and the physical demands placed on the chip. One typical rule is a minimum feature distance requirement. This rule ensures that every wire and shape is wide enough to function properly. In some systems, the minimum feature distance can include the minimum width allowed for a wire or a portion of a shape.
Unfortunately, when an edge of a wire is placed near an edge of a shape at a non-zero distance from the edge of the shape that is less than the minimum feature distance, the masking tool will assume that the part of the width of the portion of the shape between the edge of the wire and the edge of the shape violates the minimum feature distance rule. The masking tool will then add a “jog” to either the shape or the wire (or both) to achieve the minimum feature distance. The creation of jogs is sometimes referred to as the “blooming effect.”
This is shown in FIG. 1A, where a couple of wires 30 are connected to a shape 20 (in this case, the shape 20 is used to couple the wires 30 to a pair of vias 22). The resulting shape 40 on the mask created by the masking tool includes several jogs 42a and 42b that the masking tool adds to compensate for rounding of edges in the fabrication process. Some of the jogs (such as 42a) are undesirable because they not necessary to compensate for rounding and introduce extra small edges and corners, which may be detrimental to the yield of the design and require added mask compensation shapes. As shown in FIG. 1B, if the wire 30 is aligned with the shape 20, then some of the jogs 42a are eliminated. Currently, users must manually run a wire straightening program after running the wiring tool to try to reduce the number of jogs. This adds cost to the development process.
Therefore, there is a need for a wire routing tool that connects wires to shapes so as to minimize jogs.